IBM Stacks Transistors to Push Chip Density Past 2nm Limits

Demand for denser, more efficient chips to power AI systems has intensified as conventional transistor shrinking approaches fundamental physical barriers. IBM announced a prototype architecture that stacks transistors vertically in a staggered two-layer configuration, achieving roughly 100 billion transistors on a fingernail-sized area—twice the density of its 2021 2-nanometer design.

The approach, called nanostack, builds on nanosheet transistors by fabricating one layer of devices, bonding a second silicon layer, and creating another set of transistors offset from those below. IBM Research director Jay Gambetta described the result as a meaningful leap that could deliver up to 50 percent higher performance or 70 percent better energy efficiency than the prior generation. The company also reported a 40 percent improvement in SRAM scaling through the staggered layout.

Node labels such as 0.7 nanometer remain marketing conventions rather than measurements of actual feature sizes, which stay larger to avoid quantum interference. IBM does not produce chips at scale and instead licenses technology to partners including Rapidus in Japan and Samsung in South Korea; it has not named a foundry for the new architecture. Production of commercial chips using nanostack could begin within five years, according to IBM vice president Huiming Bu.

Other firms are pursuing similar vertical integration. Intel discussed 3D transistor stacking in 2023, while TSMC and Samsung have explored complementary field-effect transistors. IBM’s staggered layout and single-dielectric bonding allow independent optimization of each layer and separate front- and back-side contacts. Manufacturing hurdles remain significant: adding layers raises defect rates because failure in either tier ruins the chip, and each new layer must be processed below roughly 400 °C to protect underlying connections.

Academic groups have demonstrated lower-temperature stacking methods using junctionless transistors, though these remain proofs of concept. IBM’s work shows the technique can be executed across a full wafer in an existing production line. The central open question is whether the added process complexity can be managed at acceptable yields and costs when moving beyond prototypes.